RESUME

Anchor 1

Research
at USC

High Performance Graph Analytics
PhD Research, University of Southern California

2016 - present

Graph algorithms are infamous for their irregular parallelism and memory accesses, unlike their siblings in dense Linear Algebra. I worked on developing new data layouts and reordering schemes to improve access locality and performance of Graph Algorithms.

I am also interested in developing new parallel algorithms for analytics which are expensive and challenging to parallelize. It is a very exciting space and gives me immense satisfaction when I come up with a new idea that I can theoretically and empirically establish. Please browse the Projects page for more details on my work.

Skills

Algorithms and Analytics - theory & practice
Teaching
Scientific Reading, Debate
Cooking - must try my food, wife is a fan
Biking, tennis, badminton, cricket, skating, singing, endurance running
... And of course MS Powerpoint ;)

Work

experience

Senior Engineer, Samsung R&D Insitute Bangalore

2014-16

Before USC, most of my work was in Hardware IP and VLSI Design. Fortunately, I was a part of a small but very inspiring team at Samsung. Our work on IPs ranged all the way from algorithm development, POC, hardware design to initial verification. One of our designs on a Runtime Image Codec was presented at ISCAS, 2016.

Intern, Qualcomm Bangalore

Summer 2012

Ahh, the golden days of internship. I worked with Mr. Rajesh Arimilli who was a very driven employee in the Physical Design team. Resolving congestion in VLSI layouts used to be done manually and was time-consuming. With Rajesh, I developed a small tool for autonomous template-based Layout Congestion removal to reduce tapeout time.

The method was presented at the Synopsis Users Group Conference, 2012. We also used it to tape out some cores assigned to the team, for which I received the Qualstar Emerald Appreciation Award. Overall, loved the city, working at the company and my first salary :P

Languages

C/C++, Python
OpenMP, MPI, CUDA
Hardware Design Languages - VHDL, Verilog
Scripting - Perl, Python

Education

PhD Student, University of Southern California

2016 - present

Other than my PhD research, I also worked on Hardware acceleration for Machine Learning, Influence Propagation in Social Networks, Computer Architecture, and Network Processor designing. Through courses and projects, I have developed a deep understanding of these areas. I am a Teaching Assistant for Prof. Puvvada Gandhi's course titled "Computer Systems Organization (EE 457)".

B.Tech & M.Tech in Electrical Engineering, IIT Bombay
2009 - 2014

Learnt the ABCD of Electrical Engineering. My first exposure to a huge field of work in power systems, signal processing, communications, device physics, and circuit design.

My major work there was my Master's thesis project to develop FPGA-based HW designs as a proof of concept for low-power portable ECG analysis. This work was done under the guidance of Prof. Madhav Desai. Also had a brief stint in device physics research with Prof. Udayan Ganguly.

One of my most enriching experiences at IIT was being the Head & Mentor at Department Academic Mentorship Programme. I got to see the challenges faced by students first hand and also had an opportunity to recruit, organize and motivate very bright students for the tough job of mentoring.